K. W. Cameron, and Y. Luo, “Instruction-level Microprocessor Modeling of Scientific Applications,” Proceedings of the Second International Symposium on High Performance Computing (ISHPC 99), May 1999, pp. 29-41.
Monthly Archive for May, 1999
Y. Luo, K. W. Cameron, and O. Lubeck, Instruction-level Characterization of Computational Physics and Multimedia Applications Using Performance Counters. Proceedings of 2nd Workshop on Computer Architecture Evaluation Using Commercial Workloads (CAECW), 1999, pp. 12.
Abstract
The paper provides characterization methods based on empirical performance counter measurements. In particular, we provide an instruction-level characterization derived empirically in an effort to demonstrate how architectural limitations in underlying hardware will affect the performance of existing codes. Preliminary results provide promise in code characterization, and empirical/analytical modeling. These include the ability to quantify outstanding miss utilization and stall time attributable to architectural limitations in the CPU and the memory hierarchy. This work further promises insight into quantifying bounds for CPI0 or the ideal CPI with infinite, perfect L1 cache. In general, if we can characterize workloads using parameters that are independent of architecture, such as this work, then we can more appropriately compare different architectures in an effort to direct processor/code development